1. Field of the Invention
The present invention relates to a semiconductor storage device.
2. Background Art
The FBC (Floating Body Cell) is a volatile memory formed on a SOI substrate. It is a memory that stores data “1” or “0” depending upon whether holes are stored in a floating body of a transistor. In order to discriminate data “1” or “0” stored in a memory cell, a reference potential having a middle potential between data “1” and data “0” is generated. The reference potential is generated by short-circuiting a reference memory cell having data “1” stored therein and a reference memory cell having data “0” stored therein to each other. A sense amplifier compares a potential of data read out from a memory cell having certain information stored therein with the reference potential. As a result, it can be discriminated whether data stored in the memory cell is “1” or “0.”
Thus for generating the reference potential, a reference memory cell having data “1” stored therein and a reference memory cell having “0” stored therein are needed.
In general, in the case of data “1,” holes are already stored in the floating body and consequently the FBC memory cell is not affected by retention. In the case of data “0,” holes gradually get into the floating body because of retention and data changes to “1.” Thus, in FBC memory cells, not only memory cells having information stored therein, but also reference memory cells having data “0” used as reference potential are also affected by the retention. In order to prevent the reference potential from being varied by the retention, therefore, refresh operation is needed. This results in a problem that reduction of power dissipation in the semiconductor apparatus is difficult.
If a reference potential is generated by using the memory cell having data “1” stored therein and the reference cell having data “0” stored therein, variation occurs in the reference potential. The variation in the reference potential is the average of the variation in the reference memory cell having data “1” stored therein and the variation in the reference memory cell having data “0” stored therein. If the variation in the reference potential is large, the range of the variation in the reference potential and the variation in the memory cell overlap each other in some cases. This affects the yield of the semiconductor storage device. Therefore, it is necessary to make the width of the potential difference between data “1” and data “0” large so as to prevent the variation range of the reference potential and the variation range of the memory cell from overlapping each other. In the situation where the semiconductor storage device is made finer and finer, it is difficult to make the width of the potential difference between data “1” and data “0.”
Therefore, a semiconductor storage device including a reference memory cell, which generates a reference potential having less variation and which does not need refresh operation, is desired.